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- Responsible for all aspects of physical design and implementation of processor and other ASICs
- Participating in establishing physical design methodologies, flow automation, chip floor plan, power/clock distribution, chip assembly and P&J12, timing closure.
- Working on static timing analysis, power and noise analysis and back-end verification.
- 3+ years of experience in large VLSI physical design implementation
- Successful track record of delivering designs to production is a must.
- Should be a power user of P&R and timing analysis CAD tools
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers.
- Prior experience in Timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tape out solutions.
- Proficiency using Perl, TCL, Make scripting is preferred.
