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Power Estimation, Clock Gating, Power Gating, Power Estimation and Modeling Lead, World leader in Visual Computing Technologies

Architect and develop Power Estimation Models for key use-cases, Leakage, and IO Power. Design the tools based on these models, and develop solid validation methodology/infrastructures. Lead a team, interface/coordinate with external teams in the US and India that provides necessary input data...

Updated: 2012-May-19 01:04 AM

Industry: HardwareRole: Power Estimation and Modeling Lead

Experience Level: 3.0 to 8.0 yrsLocation: (India)

Keywords: Power Estimation Clock Gating Power Gating Multi VT/DVFS Perl/TCL/C++

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Emulation, Verilog,VHDL,System Verilog, FPGA Design, Emulation Engineer, The world's largest provider of wireless chipset technology

2-8 years industry experience -Sound knowledge in Verilog/VHDL/System Verilog -Minimum 3+ years of multi-FPGA Design Verification experience (Xilinx preferred) -Sound knowledge of Synthesis, Timing Analysis, Place-n-route tools and methodologies -Good knowledge of ARM based SOC with experience...

Updated: 2012-May-19 01:04 AM

Industry: HardwareRole: Emulation Engineer

Experience Level: 2.0 to 8.0 yrsLocation: (India)

Keywords: Emulation VerilogVHDLSystem Verilog FPGA Design Verification STA/Synthesis

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Post Silicon Validation, Soc/Microcontroller, Sr. Validation Engineer, The World's Largest Microprocessor Manufacturer

Senior Validation Engineer with prior experience in Pre-silicon validation on FPGA platforms, Post-silicon Validation and board design.More details: 1. Knowledge of ARM Cortex M cores, compilers and linkers is a must. 2. Prior validation experience in Serial communication protocols and complex...

Updated: 2012-May-19 01:04 AM

Role: Sr. Validation Engineer

Experience Level: 4.0 to 14.0 yrsLocation: (India)

Keywords: Post Silicon Validation Soc/Microcontroller

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DFT, Analog DFT, SOC, DFT Lead, World Leader in Visual Computing Technologies

DFT lead Engineer Will be responsible for Designing Implementing DFT techniques (Advanced Scan/Compression/At-speed Scan/Core based DFT) on Complex SOCs with Analog IPs to improve testability. Test vector generation (DC/AC/path delay/IDDQ/Bridging fault) with highest possible test coverage with...

Updated: 2012-May-19 01:04 AM

Industry: HardwareRole: DFT Lead

Experience Level: 3.0 to 8.0 yrsLocation: (India)

Keywords: DFT Analog DFT SOC Timing closure Sign-off

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Opportunity for Cloud Architect, Virtualization, Storage domain with a Storage giant in Bangalore

Responsibilities: Ö The Principal Architect will be required to multitask across work streams spanning PCIG infrastructure related technologies, seek commonalities between business processes for efficiencies and work to resolve inefficiencies from complex solutions related to...

Updated: 2012-May-19 01:04 AM

Industry: IT ProductsRole: Cloud Architect

Experience Level: 12.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Cloud Virtualization Storage Architect SAN NAS SCSI Raid

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Enterprise security product develper, Principle software engineer, with Storage giant in Bangalore, India

Design and development of enterprise security product with seamless integration with other products in the organization’s portfolio of solutions Accountable for delivery of subsystem, anticipate issues and addresses proactively. Writes high level design specs, unit test plans and integration...

Updated: 2012-May-19 01:04 AM

Industry: IT ProductsRole: Principle software engineer

Experience Level: 8.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Security product develpment high level design specs unit test planning enterprise product development Security concepts Storage and security protocols

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File system development opportunity with Storage giant for Bangalore

Principal Responsibilities Design and code software using the established development process. Unit test, debug and correct defects Generate appropriate documentation for the design and implementation of the software modules, and the proper ongoing support of software modules Participate in...

Updated: 2012-May-19 01:04 AM

Industry: IT ProductsRole: File system development

Experience Level: 3.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: File system Kernel development Storage SAN / NAS SCSI / Raid System programming

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C/C++, Field Application Engineer, Silicon Chip Company - leaders in DSP

Job Description Required Basic Qualifications: 4 to 8 years of work experience in Microcontroller/DSC applications, Good Knowledge of writing software programs in C/C++ language, Hands-On experience, Systems knowledge on development for couple of End Equipments/applications, Good Communication...

Updated: 2012-May-18 01:07 AM

Industry: SemiconductorRole: Field Application Engineer

Experience Level: 4.0 to 10.0 yrsLocation: (India)

Keywords: C/C++

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Java, Security, Oracle, Consultant Software Engineer, The Leaders in Network, Storage and Cloud Computing

Consultant Software Engineer DESIGNATION: Consultant Software Engineer EDUCATION: BE / BTech / MTech from CS background PRINCIPAL DUTIES AND RESPONSIBILITIES Architecture and design of Key Management products with seamless integration with other products in Security’s portfolio of...

Updated: 2012-May-18 01:07 AM

Industry: IT ProductsRole: Consultant Software Engineer

Experience Level: 13.0 to 19.0 yrsLocation: (India)

Keywords: Java Security Oracle Identity/Access management PKI/Cryptography Electronic Signature

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Business Development Manager Online jobs bangalore

Key Responsibilities: Lead - Hiring, Managing a category team distributed across the country - The team Execute - Strong bias for Action : Company works at a very rapid pace that is what would be expected from the category function as well - Recognise sources and set up Vendor Accounts for...

Updated: 2012-May-17 01:07 AM

Role: Sr, Manager

Experience Level: 2.0 to 6.0 yrsLocation: (India)

Keywords: Business Development/sales Sales

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Job Opening for Physical Design Engineers

- Responsible for all aspects of physical design and implementation of processor and other ASICs - Participating in establishing physical design methodologies, flow automation, chip floor plan, power/clock distribution, chip assembly and P J12, timing closure. - Working on static timing...

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Job Opening for Physical Design Engineers

Experience Level: 2.0 to 8.0 yrsLocation: (India)

Keywords: Physical Design Back-End Design STA

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Job Position for Senior Physical Design Engineers

'Responsible for designing, developing, modifying and evaluating electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data, conducts experimental tests and...

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Job Position for Senior Physical Design Engineers

Experience Level: 2.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: Physical Design Back End Design

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Vacancies for RTL Design, Logic Design / Front End Design Engineer

IP design development for Memory controllers, Mixed-Signal IP and pure digital IP development for MSP430 or ARM Cortex™-R core based SoCs. Ownership of Complete IP development activity involving Concept development, RTL, synthesis, Lint Equivalence check, etc. Handling IP process requirements....

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: RTL Design, Logic Design / Front End Design Engineer for the World leaders in Microprocessor Chip

Experience Level: 3.0 to 8.0 yrsLocation: (India)

Keywords: ASIC Design RTL Design Front End Design

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Opening for ASIC Design Engineer

In this position, the candidate will be responsible for design of soft IP cores for the next generation chips (including SOCs) for the different market segments.

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: ASIC Design Engineer for the World leaders in Microprocessor Chip

Experience Level: 4.0 to 10.0 yrsLocation: Bangalore (India)

Keywords: ASIC Design Front End Design RTL Design

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Opening for RTL Design

'Primary and Secondary Responsibilities: Design and Validation of RTL for Digital Power Supply Controller IC for Server CPU and Memory Applications.Ownership of all Digital Designs for CPM world-wide Team Complex Tasks: (a) Digital Design Implementation (RTL Coding, synthesis, ATPG, Static...

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Logic Design Front-End Design RTL Design

Experience Level: 4.0 to 8.0 yrsLocation: (India)

Keywords: Logic Design Front End Design ASIC Design

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Opening for Director Hardware Engineering

•To lead the design team comprising of 50+ Engineers working on state of the art ASIC implementations for connectivity products including WLAN Access Points/Routers, STBs,etc •Drive the large HW teams involved in various activities including: RTL, Digital Validation, HW Emulation, RF, Chip...

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Director Hardware Engineering

Experience Level: 15.0 to 25.0 yrsLocation: (India)

Keywords: ASIC Design ASIC Verification SOC Design

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opening for STA Engineer

will work on STA using Synopsys timing tools. Should be able to work independently on: a. Functional timing constraints b. Timing analysis and fixes c. Understanding of Max load / cap / trans violations and fixes d. Understanding of impact of signal integrity on timing

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Static Timing Analysis

Experience Level: 2.0 to 6.0 yrsLocation: (India)

Keywords: STA PD Timing

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opening for Senior Synthesis and STA Engineer

* Own/drive the STA and timing closure activities for the design. * Use of Synopsis DC Synopsys Primetime tools and Primetime SI tools * Use of Cadence RC and ETS * Write simple scripts to process the reports, come up with ECO etc., * Timing closure for full chip SoC design.

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Synthesis and Static Timing Analysis (STA)

Experience Level: 4.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: Synthesis STA Timing

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job opening for DFT Engineer

will work independently on: a. SOC and IP level DFT architecture and design b. Speed Scan ATPG and TFT implementation and verification c. PBIST / IDDQ / DC Para verification d. Coverage analysis e. Test constraints and DFT STA

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: DFT / Design for Testing

Experience Level: 2.0 to 6.0 yrsLocation: Bangalore (India)

Keywords: DFT

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opening for Analog Design Engineer

Design of PLL, oscillators, ADC, DAC Primary and Secondary Responsibilities: Be responsible for completing block designs Complex Tasks: Should be well versed with Silicon Debug at the block level Management/Organizational Skills: Schedule bound

Updated: 2012-May-17 01:07 AM

Industry: HardwareRole: Analog Design

Experience Level: 2.0 to 6.0 yrsLocation: Bangalore (India)

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Recent Jobs

Keywords: Power Estimation Clock Gating Power Gating Multi VT/DVFS Perl/TCL/C++

Keywords: Emulation VerilogVHDLSystem Verilog FPGA Design Verification STA/Synthesis

Keywords: Post Silicon Validation Soc/Microcontroller

Keywords: DFT Analog DFT SOC Timing closure Sign-off

Keywords: Cloud Virtualization Storage Architect SAN NAS SCSI Raid

Keywords: Security product develpment high level design specs unit test planning enterprise product development Security concepts Storage and security protocols

Keywords: File system Kernel development Storage SAN / NAS SCSI / Raid System programming

Keywords: C/C++

Keywords: Java Security Oracle Identity/Access management PKI/Cryptography Electronic Signature

Keywords: Business Development/sales Sales

Keywords: Physical Design Back-End Design STA

Keywords: Physical Design Back End Design

Keywords: ASIC Design RTL Design Front End Design

Keywords: ASIC Design Front End Design RTL Design

Keywords: Logic Design Front End Design ASIC Design

Keywords: ASIC Design ASIC Verification SOC Design

Keywords: STA PD Timing

Keywords: Synthesis STA Timing

Keywords: DFT

Keywords: Analog CMOS AMS